1. Field of the Invention
The present invention relates to content addressable memory (CAM) devices, and more particularly to power and area saving methods for CAM integrated circuits (IC).
2. Description of the Prior Art
Content address memory (CAM) is a useful device for executing table lookup operations. Particularly, because of the parallel lookup capability, a user can execute thousands or even millions of comparisons with one lookup operation.
For computer systems, CAM is widely used as the address lookup table (called cache TAG) for cache memory, or as the paging translation look-aside table (TLB). These CAM devices for computer applications are relatively small comparing to other IC components, so that the cost and power consumption are relatively insignificantly in a computer system.
For communication applications, CAM is widely used to support address lookup operations for routers. Recently, the rapid growths of networking systems triggered strong demands for high density and high speed CAM devices. A typical current art CAM for networking application has 256K of 72 bit entries supporting 125 million lookups per second (LPS). However, due to the parallel lookup operation of CAM devices, the power consumption of a CAM device increases linearly with its density and lookup rate. In the mean time, the cost of each CAM device increases exponentially with its area. The power consumption and costs of CAM devices are becoming the limiting factors for current art router systems. It is simply too expensive and requires too much power to put enough CAM devices on router systems to support desired performances. It is therefore an urgent need to provide power and area reduction methods for high-density CAM devices.